Spi - TheTaoOfFieldbus

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Serial Peripheral Interface
Hercules TMS570LC43x LaunchPad Development Kit

This paper is going to explain some features about the slave side. Step to Step it dives to analyze all the points that are important to get a complete EtherCAT slave working. It will start with some development kits, in this tutorial it has been selected the TMS570LC43x Launchpad, for following reasons :

a) Price
b) Powerfull microcontroller
c) Different plugs Booster Packs and motion controls
d) No limitation for the kit version of the
Code Composer



In this part, has been reported the intials tools for running the code:

1) Code Composer, that can be download from Texas Instruments website link

2) Evaluation Board Kit : Hercules LaunchXl2-570LC43

3) Piggyback Controller : FB1111-141


4) Power Supply 5V
HW Signals Wiring


The beginning of this part has been started with the Schematics description of the Hercules. Three headers have to be considered:


Header J3
Pin1 : Power Supply 5 Volt => Input



Header J1
Pin7 : SPI_CLK => Output




Header J2
Pin1 : Power Supply Gnd => Input
Pin6 : SPI_SIMO =>Output
Pin7 : SPI_SOMI =>Input
Pin8 : SPI_CS =>Output

The following shows the Schematic description of the Piggyback FB1111-141 (SPI).




Header

Pin1  : Power Supply Gnd => Input
Pin10 : Power Supply Gnd => Input
Pin19 : Power Supply Gnd => Input
Pin28 : Power Supply Gnd => Input
Pin37 : Power Supply Gnd => Input
Pin46 : Power Supply Gnd => Input
Pin47 : Power Supply 5 Volt => Input
Pin49 : Power Supply 5 Volt => Input



Pin22 : SPI_CS => Input
Pin29 : SPI_SIMO => Input
Pin31 : SPI_SOMI =>Output
Pin38 : SPI_CLK => Input



The next step is to plug all toghter. it has need to consider that the Hercules is the SPI Master and FB1111-141 is the SPI Slave.

Intentionally  it doesn't implement all the signals (ISR). This specific topic will be the matter on the next tutorials.

Spi Protocol Specification



This segment describes the Spi protocol in order to open a communication channel between the two devices. The reference manual is ET1100 Hardware Data Sheet .
The ESC (EtherCAT Slave Controller) defines two different area: Registers Area and Memory Area. The first is mandatory and it is fixed to 4Kb and The second is elastic. It depends by the implementation. In any case also for the second one there is a max limit set to 60Kb.
The sum of both area is , in the worst case, equal to 64Kb.

In order to access the whole memory zone, two parameters have to be definded: Address and Command.
Of course, it can not trasmit them in randomic way, the slave is not so smart to decipher. For this purpose the protocol establishes the order of the bytes and the content to get success.


The commands have been defined and described below :
CMD[2]
CMD[1]
CMD[0]
Command
000
NOP (no operation)
001
reserved
010
Read
011
Read with following Wait State bytes
100
Write
101
reserved
110
Address Extension (3 address/command bytes)
111
reserved

The meaning related to the CMD[x] (x := 0,1,2), it is linked to the bit position of the command.

If the bit position has been translated in decimal number, following table will be reach.
CMD[2]
CMD[1]
CMD[0]
Value
Command
00
0
0
NOP (no operation)
00
1
1
reserved
01
0
2
Read
01
1
3
Read with following Wait State bytes
10
0
4
Write
10
1
5
reserved
11
0
6
Address Extension (3 address/command bytes)
11
1
7
reserved


2 Bytes Address Mode

Normally the spi frame is composed by the address plus command and the final byte to terminate the communication.

The minimum frame to read the first Register is based on three bytes so splitted in bits:

A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] CMD[2] CMD[1] CMD[0] B[7] B[6] B[5] B[4] B[3] B[2] B[1] B[0]


Totally there are 24 bits (3 bytes).

When two bytes address have been used (13 bits are reserved for address, 3 bits for the command)=> it can be accesses only to 2^13 = 8192 bytes = 8Kb (not more)


3 Bytes Address Mode

In order to access 64 Kb there is need to work with three bytes address. The schema is similar to the previous.

A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] F[2] F[1] F[0] A[15] A[14] A[13] CMD[2] CMD[1] CMD[0] R[1] R[0] B[7] B[6] B[5] B[4] B[3] B[2] B[1] B[0]


The bits F[2]/F[1]/F[0] are constant and equal to 110b (binary)
The bits R[1]/R[0] (reserved) are constant and equal to 00b (binary)
In this case the address bits are 16 => it can be access 2^16 = 65536 = 64*1024 = 64Kb

The Piggyback supports different spi modes. The default is mode 3.

If there is some doubt about the spi settings it is enough to read the EEPROM word 0 e word 1 (Reg 0x140/0x141/0x150/0x151).



Frame Analysis

This part shows the devices in action. The first test is to read the whole regs area (4Kb). Each time the code reads a chunk of 256 bytes.

The result is as the follow:

The speed of SPI is 1Mhz => 1 µs for each single bit. It reads 4Kb = 4096 bytes => 4096 * 8 = 32768 bits = 32.768 µs

It reads every time 256 bytes => 4000/256 = 16 => 16 * 2 (Address + Cmd bytes) = 32 * 8 = 256 bits more caused by preamble

Theoretically the final access time is  about 33 ms. It has been to add  the delay caused by the trasmission of each single byte (as shown below and in the following analysis). If it has been add just 4000 (bytes ) * 1.5 µs  the total times to add becomes 6 ms .
The total access time is now 33 + 6 = 39 ms, nearest to the oscilloscope measurament.

Example: Read single byte at  address 0x400

In this examples, it has been send three bytes, as it has been explained before.
The command is a Read => it means  value  2
The address is 0x400
The final byte is 0xFF , it means stop to read sequentially. If it is different from 0xFF => the next byte is relative to the next address (0x401)

A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] CMD[2] CMD[1] CMD[0] B[7] B[6] B[5] B[4] B[3] B[2] B[1] B[0]
                                                                                                                  

A[12] = 0         CMD[2] = 0       B[7] = 1
A[11] = 0         CMD[1] = 1       B[6] = 1
A[10] = 1         CMD[0] = 0       B[5] = 1
A[9] = 0                                    B[4] = 1
A[8] = 0                                    B[3] = 1
A[7] = 0                                    B[2] = 1
A[6] = 0                                    B[1] = 1
A[5] = 0                                    B[0] = 1
A[4] = 0
A[3] = 0
A[2] = 0
A[1] = 0
A[0] = 0

The Address byte A[12] is the first to be transmitted => 1 byte (high value address), 2 byte (low value address + CMD), 3 byte (0xFF , the trasmission is closed)
The green line is the reply of the SPI slave.

REPLY[7] = 1
REPLY[6] = 1
REPLY[5] = 0
REPLY[4] = 0
REPLY[3] = 0
REPLY[2] = 0
REPLY[1] = 1
REPLY[0] = 0

Reply Byte = 11000010b=0xc2 (low party Watchdog Divider)      


Here, has been shown the edges of the different signals in details. Some notes relative to the first bit of the SOMI, it is set to one and it means that the last command was executed with success. It has been mentioned also the CS , it starts and closes the whole communication. The negative edges of the clock control the whole communication. The trace fits with what has been documented in the official manual ET1100.


Software Description

The complete code to generate and to run the examples has been included in this part. It has started with HalCoGen to setup quickly the hw, but It has been modified many parts included the SPI function in order to read/write. The original code was not suitable for the final purposes.

Every data structure is splitted in bytes and bits and it is relative to the whole registers Area.

Next the project has been the folders dedicated to the Hardware of the Hercules (HwCfgTexas) and the folders relative to EtherCAT side.

following the log files related to the registers (plain form) have been proposed with the data structures values:
Copyright notice
The website and its content is copyright of Nicola Urbano - ©Nicola Urbano -2010. All rights reserved.
Any redistribution or reproduction of part or all of the contents in any form is prohibited without to contact the Author
Wireshark and the "fin" logo are registered trademarks of the Wireshark foundation. EtherCAT® is registered trademark of ans licensed by Beckhoff Automation GmbH
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